1. Field of the Invention
The present invention relates to the field of semiconductor thin films; and more particularly to novel polycide thin films and their methods of fabrication.
2. Discussion of Related Art
Polycrystalline silicon (polysilicon) is a thin film which has been widely used in semiconductor manufacturing. Polysilicon lines have been used as gate electrodes, interconnects, and capacitors in integrated circuits. Polysilicon, however, has been somewhat limited by its high bulk resistivity. Polycide films which consist of a low resistance silicide formed on a doped polysilicon film have been used in place of polysilicon in an attempt to decrease the resistance of gate electrodes and interconnects to thereby create faster and lower power consuming integrated circuits.
A current method of fabricating a polycide gate electrode utilizing a self-aligned silicide (salicide) process is illustrated in FIGS. 1a-1c. According to a standard salicide process, a conventional transistor, such as the N-channel metal oxide semiconductor field effect transistor (NMOSFET) shown in FIG. 1a is provided. NMOS transistor 100 has a polysilicon gate electrode 104 formed on a gate dielectric 102 which in turn is formed on a p-type monocrystalline silicon substrate 101. Spacers 106 are formed adjacent to and run along opposite sidewalls of polysilicon gate electrode 104. N- source/drain tip regions 108 and N+ source/drain contact regions 110 are formed into substrate 101 in alignment with polysilicon gate electrode 104 and sidewall spacers 106, respectively.
In order to reduce the resistance of polysilicon gate electrode 104 and source/drain contact regions 110, a metal layer 112 such as titanium, is blanket deposited over substrate 101, as shown in FIG. 1b. Substrate 101 is then annealed to cause a reaction between titanium layer 112 and exposed silicon on polysilicon gate electrode 104 and source/drain contact regions 110 to form low resistance titanium-silicide (TiSi.sub.x wherein X.apprxeq.2) 114. No silicide reaction occurs on spacers 106 because no silicon is available for reaction with titanium. Next, as shown in FIG. 1c, unreacted titanium is removed from spacers 106 with an etchant which preferentially etches titanium as opposed to titanium-silicide. The result is a low resistance silicide 114 which has been selectively formed on the source/drain contact regions 110 and on the top of polysilicon gate electrode 104.
A problem with the silicide process described above is that it cannot be reliably used to form silicides on narrow polysilicon gate electrodes (i.e. gate lengths less than 0.25 .mu.m). During the annealing of substrate 101, silicon and titanium first react to form what is known as C-49 titanium-silicide. C-49 titanium-silicide has a relatively high resistance and must subsequently be converted into C-54 titanium-silicide which has a substantially lower resistance. C-49 titanium-silicide is converted into C-54 titanium-silicide by initiating the formation of a C-54 nucleation site or island from which the remainder of the C-49 film can convert into C-54 titanium-silicide. As gate lengths decrease, higher C-54 nucleation densities are required in order to ensure the formation of a C-54 nucleation site on the gate electrode so that the remainder of the C-49 titanium-silicide on the gate electrode can convert into C-54 titanium-silicide. Nucleation density is increased by increasing the annealing temperature of the silicide process. Thus, as gate electrode dimensions decrease, anneal temperatures must increase in order to provide a high enough nucleation density to insure that a low resistance silicide can be formed on narrow lines.
Unfortunately, however, at high anneal temperatures, silicides become unstable and begin to agglomerate or "bubble" 116 which causes dislocations and discontinuities 118 in the silicide. FIG. 1d is an illustration of the agglomeration of a silicide viewed along the "width" of a gate electrode. Dislocations and discontinuities 118 in a silicide on a gate electrode can cause a substantial increase in the resistance of the gate electrode which reduces device performance and basically defeats the purpose of forming a silicide in the first place.
As such, the silicide process described above has a thermal window in which a low resistance and uniform polysilicide film can be reliably formed. The silicide process must exceed a minimum temperature in order to provide a high enough nucleation density to ensure the formation of a low resistance silicide on narrow gate electrodes (or polysilicon lines), and must remain below a maximum temperature in order to prevent silicide agglomeration. Thus, as polysilicon gate lengths decrease to fabricate higher density integrated circuits, (i.e. as polysilicon lines become narrower), the thermal window will become so small that uniform, low resistance silicides can no longer be manufacturably fabricated with such a process.
Thus, what is needed is a method of increasing the thermal stability of silicide films.